when we create FSM in verilog there are usually two methods to write FSM very first is using 3 often prevent(1 for next-state combinational reasoning + 1 for presene-gt;next state sequential reasoning + 1 for output reasoning) and second way is usually to use only one generally wedge for all 3 procedure but my result influx for both situations is different.why can be it so?
for example i possess coded simple fsm in both ways and my out is shifted by 20 timeunit
![Serial Adder Moore Model Verilog Serial Adder Moore Model Verilog](/uploads/1/2/5/0/125004395/413526098.png)
4 Bit Serial Adder Verilog Code For Full DOWNLOAD a1e5b628f3 4 Bit Ripple Carry Adder in Verilog. A,B); endmodule Structural Model: Full Adder module fulladder. I need 16-bit ripple carry adder testbench verilog code.4-bit Full Adder using Two 2-bit Full Adders. Unorthodox but I'm curious to know as I am new to Verilog.
1st way :
2nd method
why the result is shifted by 20 timeunit.?
user3091069user3091069
1 Answer
I have always been going to create a several assumptions about how you are tests both of these, specifically that you possess something like this in your testbench:
And I feel also supposing the second way is usually 20 (or probably 19?) period units ahead of the initial way, based on what I believe is heading incorrect.
Generally, the initial way is usually streaming the output
yout
in a sign up while the 2nd way is certainly placingyout
combinationally.As this is certainly a Moore device (which both of those implementations are usually), the result is reliant only on the current condition. In the very first method, on the clock edge,
yout
is being established to a worth based on the 'present' condition (web browser, what the state is definitely the second best before the clock edge). While the state might furthermore change at the clock edge, this will not occur until after the next worth ofyout
provides been identified for this clock routine. This indicates in a individual clock cycle,yout
will end up being set centered on what the state had been in the prior routine and stay that method until the following clock edge.In the 2nd method,
yout
will be arranged combinationally instead than on a clock edge. In this situation, the following state logic will determinestate
and when a clock edge comes together,nextstate
will turn out to becondition
(after 1 period device for some reason.). Thus, now the combinational block that decides the outputyout
will wake upward and fixedyout
to whatever value for that state. Thus,yout
will get on the result for the current condition, the condition for this clock routine and not that of the previous clock routine as in the first method.For instance, state we're in state
t1
andxin
is definitely asserted. Thus, in the 2nd waycondition
is all ready atbeds2
in preparation for the changeover. A clock edge arrives.In the 1st way, the always block wakes up.
reset
isn'capital t asserted therefore on to the situation declaration. We're ins1
andxin
can be asserted sostate
will turn out to bet2
andyout
is usually set to 0. Done until the following clock advantage. So it will appear like we are ins i90002
andyout
is definitely 0, until the following clock edge, at which periodyout
will turn out to be 1.In the 2nd way, the condition register always obstruct wakes up and
nextstate
getss2
after 1 period unit. Oncenextstate
gets to bet2
, the output logic constantly block out foryout
will wake up up and todaynextstate
will bes i90002
soyout
will become 1 now (or again after 1 time unit?). So it will look like we are usually ins i90002
andyout
will be 1 (roughly), which is usually about 20 time units forward.![Verilog Verilog](/uploads/1/2/5/0/125004395/727241696.png)
Notice: Very much of the confusion involved in this (partially as Tim mentioned) can be not especially good style. I choose the 2nd way even more, but the way you implemented it is certainly relatively non-ideal. Heres a suggested spin for upcoming referrals (though I do get some simplification protections as properly):
Hope this helps you realize better!
UnnUnn
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when we create FSM in verilog there are usually two ways to compose FSM very first is making use of 3 usually block(1 for next-state combinational logic + 1 for presene-gt;next state sequential reasoning + 1 for result reasoning) and second way can be to make use of only one generally block for all 3 operation but my output wave for both cases is different.why is definitely it so?
for illustration i possess coded easy fsm in both methods and my out there is altered by 20 timeunit
1st method :
2nd method
why the output is altered by 20 timeunit.?
user3091069consumer3091069
1 Reply
I was going to create a several assumptions about how you are usually examining both of these, specifically that you possess something like this in your testbench:
And I are also presuming the 2nd way is 20 (or maybe 19?) period units forward of the initial way, based on what I think is heading incorrect.
Fundamentally, the very first way can be buffering the result
yout
in a sign up while the 2nd way will be establishingyout
combinationally.As this is certainly a Moore device (which both of those implementations are usually), the output is reliant just on the present condition. In the initial way, on the clock advantage,
yout
is certainly being established to a value based on the 'present' condition (ie, what the condition can be the second best before the time clock advantage). While the condition might also change at the time clock advantage, this will not really happen until after the next worth ofyout
provides been motivated for this clock cycle. This indicates in a solitary clock routine,yout
will end up being set based on what the state was in the previous routine and stay that way until the following clock advantage.In the 2nd method,
yout
can be arranged combinationally instead than on a time clock edge. In this situation, the following state logic will figure outcondition
and when a time clock edge comes along,nextstate
will turn out to becondition
(after 1 time device for some reason.). Thus, today the combinational engine block that establishes the outputyout
will wake up and arrangedyout
to whatever worth for that condition. Thus,yout
will consider on the output for the current state, the condition for this clock cycle and not really that of the prior clock routine as in the first method.For example, say we're also in state
beds1
andxin
is certainly asserted. Hence, in the second methodstate
is usually all prepared ath2
in planning for the transition. A clock edge arrives.In the initial method, the always stop wakes up.
reset to zero
isn'capital t asserted so on to the case statement. We're inh1
andxin
will be true sostate
will turn out to bes2
andyout
is certainly established to 0. Done until the next clock advantage. So it will look like we are usually inbeds2
andyout
is usually 0, until the following clock edge, at which timeyout
will turn out to be 1.In the second method, the state register continually obstruct wakes up and
nextstate
gets to bes i90002
after 1 period unit. As soon asnextstate
gets to bes i90002
, the result logic usually wedge foryout
will wake up upward and right nownextstate
can beh2
soyout
will become 1 now (or once again after 1 time unit?). So it will look like we are int2
andyout
is certainly 1 (roughly), which is usually about 20 time units forward.Take note: Very much of the dilemma included in this (partially as Tim talked about) is definitely not particularly good style. I prefer the 2nd way more, but the method you applied it will be relatively non-ideal. Heres a suggested spinning for future reference (though I did take some simplification protections as nicely):
Wish this helps you understand much better!
UnnUnn